1. Field of the Invention
This invention generally relates to a standard delay format (SDF) file, and more particularly, to a method of generating a protected SDF file.
2. Description of Related Art
As the semiconductor manufacturing technology advances, the integrated circuit (IC) becomes the most important electronic devices for all equipment. To simplify the IC design process, a variety of computer aided design (CAD) tools have been developed to aid the designer to design the IC.
FIG. 1 is a typical IC design flow chart. Referring to FIG. 1, the IC designer will use the high-level language such as Vernlog or VHDL to describe the function of the IC and create the RTL file 110. The RTL file 110 is then inputted to the synthesizer 120 and is converted into the netlist 140 in the cell level based on the library 130 provided by the semiconductor foundry. The netlist 140 includes the cells for providing the function of the IC and describes the interconnection between those cells for the layout.
To simulate and verify the function of the IC before the IC are manufactured, the IC designers will use the delay calculator 150 based on the netlist 140 and the timing library 160 to generate the SDF file 150 for the simulator 190 to verify. The SDF file 170 generally includes the cell delay description and the interconnect delay description. The cell delay description describes the signal transmission delay data on the cell I/O path. The interconnect delay description describes the signal transmission delay data of the interconnection between the cells. These signal transmission delay data are estimated values before the layout is complete. After the layout is complete, the precise signal transmission delay data can be calculated by referring the extracted RC data 145 from the RC extractor. The extracted RC data 145 is the physical resistor and capacitor data extracted by the RC extractor. Then the simulator 190 outputs the simulation result based on the netlist 140, the SDF file 170 and the simulation model 180.
As shown above, the netlist and the SDF file include the data regarding the cells and the interconnection between the cells. If those files are not protected, an unauthorized person can obtain the complete IC design by reverse-engineering. Generally, the netlist can be generated as the binary format for protection. However, the SDF file is represented by ASCII format and cannot be effectively protected.